The present invention relates to an output buffering circuit, and particularly to a H-bridge circuit used to control motor or the like, which is designed to provide direct microprocessor interface to low voltage motors.
Such a semiconductor device is known from David Cave, David Soo, T. Sakurai, M. Kojima and S. Utsumi, "Smartpower Motor Driver For Low Voltage Applications" IEEE 1987 Custom Integrated Circuits Conference. As shown in FIG. 1, one example of the device is composed of four N-channel MOS transistors 5 to 8 connected as an output buffering H-bridge circuit. To explain it in detail, the device shown in FIG. 1 comprises a control circuit 11 for feeding a first internal input terminal 12 and a second internal input terminal 13 and a H-bridge circuit composed of a first N-channel MOS transistor 5 having a drain connected to a terminal 3 of power source, a source connected to a first output terminal 9, a gate connected to the first internal input terminal 12, a second N-channel MOS transistor 6 having a drain connected to a first output terminal 9, a source connected to a terminal 4 of ground and a gate connected to the second internal input terminal 13, a third N-channel MOS transistor 7 having a drain connected to the terminal 3 of power source, a source connected to the second output terminal 10 and a gate connected to the second internal input terminal 13, and a fourth N-channel MOS transistor 8 having a drain connected to the second output terminal 10, a source connected to the terminal 4 of ground and a gate connected to the first internal input terminal 12. The first output terminal 9 is connected to the second output terminal 10 through a load. The above control circuit 11 has a terminal of power source 2, a terminal 4 of ground and an input terminal 1.
FIG. 2 is a characteristic curve of shoot-through current flowing in said device shown in FIG. 1.
Then, the operation of the semiconductor device shown in FIG. 1 is explained with reference to FIG. 2.
When electric potential of the first internal input terminal 12 is high, the first N-channel MOS transistor 5 and the fourth N-channel MOS transistor 8 becomes conductive. Therefore electric potential of the first output terminal 9 approaches about V.sub.M while electric potential of the second output terminal 10 approaches about 0 V. On the other hand, when electric potential of the second internal input terminal 13 is high, the second N-channel MOS transistor 6 and the third N-channel MOS transistor 7 become conductive. Therefore electric potential of the first output terminal 9 approaches about 0V while electric potential of the second output terminal 10 approaches about V.sub.M.
Electric potential of the first internal input terminal 12 and that of the second internal input terminal 13 are controlled by the control circuit 11 so as not to become high at the same time. However, when the above-mentioned output buffering H-bridge circuit is composed of four N-channel MOS transistors as described hereabove the switching speed of the MOS transistor on source power source side is slow as compared with the switching speed of the MOS transistor on the ground side, the MOS transistor 5 on the power source side and the MOS transistor 6 on the ground side become conductive at the same time; therefore shoot-through current flows from the terminal 3 of the power source to the terminal 4 of the ground through the first and second N-channel MOS transistors 5, 6 which results in the consumption of electricity corresponding to the shadowed portion shown in FIG. 2.
The above-mentioned conventional semiconductor device has a disadvantage that because of the difference in the switching speeds between the transistor on the power source side and the transistor on the ground side, the shoot-through current flows in the H-bridge circuit, therefore the amount of the consumed electricity in the H-bridge circuit increases. Further, the above-described device has a disadvantage that because of the shoot-through current, a big spike noise is produced at the terminal 3 of the power source and at the terminal 4 of the ground, and malfunction of the integrated circuit occurs.